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Top Tech Jobs & Startup Jobs in Austin, TX

Reposted YesterdaySaved
In-Office
5 Locations
107K-190K Annually
Expert/Leader
107K-190K Annually
Expert/Leader
Semiconductor
Oversee the design and maintenance of the VCDX Program, conduct certification panels, and develop VCDX-level content aligned with business strategies.
4 Days AgoSaved
In-Office
2 Locations
127K-226K Annually
Senior level
127K-226K Annually
Senior level
Semiconductor
Lead the development of the vSGA Stack for hypervisors, focusing on Graphics programming and GPU Driver Development, while collaborating on performance optimizations and troubleshooting.
Top Skills: CDirect3DGitOpenglShader LanguagesVulkan
Reposted 5 Days AgoSaved
In-Office
6 Locations
188K-300K Annually
Expert/Leader
188K-300K Annually
Expert/Leader
Semiconductor
Lead the vSphere Kubernetes Service Application Engineering organization, guiding customer engagements, driving Kubernetes adoption, and building a top application engineering team.
Top Skills: AksCi/CdContainersDevOpsEksGkeKubernetesReactRhosSpringVmware Cloud Foundation
Reposted 9 Days AgoSaved
In-Office
3 Locations
141K-226K Annually
Senior level
141K-226K Annually
Senior level
Semiconductor
The role involves designing flip-chip-BGA packages for ASICs, collaborating on designs, managing projects, and improving processes.
Top Skills: Allegro Package DesignerCadence ApdCadence SkillDesign Automation
15 Days AgoSaved
In-Office
2 Locations
108K-192K Annually
Senior level
108K-192K Annually
Senior level
Semiconductor
Design high-speed Serdes products through DSP engineering, focusing on algorithms, system models, and collaboration with analog/digital designers for production validation.
Top Skills: C/C++Clock And Data Recovery (Cdr)Dsp AlgorithmsMatlabRtl CodingSerdes Standards
15 Days AgoSaved
In-Office
River Hills, Austin, TX, USA
52K-83K Hourly
Senior level
52K-83K Hourly
Senior level
Semiconductor
Responsible for front end design and verification of ASIC design blocks, including architecture definition, logic design, synthesis, and verification through simulation and analysis of timing.
Top Skills: Cadence ConformalCadence Rtl CompilerGitPerlPrimetimeSpyglass LintSvnSynopsys Design CompilerSynopsys FormalityTclVerilog
15 Days AgoSaved
In-Office
River Hills, Austin, TX, USA
108K-173K Annually
Senior level
108K-173K Annually
Senior level
Semiconductor
The Analog Layout Designer will provide onsite support for advanced nodes, coordinate layout design, and work independently on various analog layout modules for deep sub-micron processes.
Top Skills: Cadence ToolsTsmc Processes
15 Days AgoSaved
In-Office
River Hills, Austin, TX, USA
108K-173K Annually
Senior level
108K-173K Annually
Senior level
Semiconductor
Responsible for various DFT aspects, including MBIST, scan insertion, yield improvement, ATE pattern development, and silicon debugging.
Top Skills: AteAtpgDftDigital LogicMbistMentor TessentPerlSynopsys
Reposted 21 Days AgoSaved
In-Office
2 Locations
127K-226K Annually
Expert/Leader
127K-226K Annually
Expert/Leader
Semiconductor
The Principal Kubernetes Software Engineer will develop and manage Kubernetes features, lead software projects, and guide teams in open source contributions. They will ensure system compatibility, mentor engineers, and collaborate with stakeholders to improve Kubernetes distributions.
Top Skills: AlgorithmsCloud PlatformsCncf ProjectsDatabasesDistributed SystemsGoKubernetesOperating SystemsVsphere
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