Top Tech Jobs & Startup Jobs in Austin, TX

11 Days AgoSaved
In-Office
River Hills, Austin, TX, USA
144K-230K Annually
Expert/Leader
144K-230K Annually
Expert/Leader
Software • Semiconductor • Manufacturing
Design complex flip-chip BGA packages for high-performance ASICs used in AI, networking, HPC, and 5G applications. Responsibilities include package layout, signal and power integrity, thermal performance, reliability, manufacturability, project scheduling, customer interface, and collaboration with internal and vendor teams. The role also supports process improvement, documentation, automation, and multi-project execution.
Top Skills: 5G Rf/MicrowaveAdc/DacAsicCadence AllegroCadence ApdCadence SkillDdr5Flip-Chip BgaHbmPower IntegritySerdesSignal Integrity
17 Days AgoSaved
In-Office
River Hills, Austin, TX, USA
151K-241K Annually
Expert/Leader
151K-241K Annually
Expert/Leader
Software • Semiconductor • Manufacturing
Lead the architecture, deployment, and scaling of agentic AI infrastructure for embedded memory design, characterization, DFT, silicon bring-up, and yield optimization. Develop multi-agent LLM workflows, integrate AI systems with EDA tools and enterprise data, automate scan-failure analysis, build predictive yield models, and establish evaluation, testing, and safety guardrails. Collaborate with memory designers, DFT experts, EDA specialists, and infrastructure engineers to deliver production-grade AI engineering solutions.
Top Skills: Agent SkillsCadence EdaCloud-Native OrchestrationDockerElectronic Design Automation (Eda)Function CallingKubernetesLanggraphLarge Language Models (Llms)MicroservicesModel Context Protocol (Mcp)Multi-Agent OrchestrationPythonRest ApisRetrieval-Augmented Generation (Rag)Siemens EdaSynopsys EdaSystemverilogTclUvmVector Databases
One Month AgoSaved
In-Office
River Hills, Austin, TX, USA
144K-230K Annually
Expert/Leader
144K-230K Annually
Expert/Leader
Software • Semiconductor • Manufacturing
Develops and deploys Calibre verification decks for advanced FINFET, GAA, and high-voltage technologies. Defines tool acceptance criteria, creates IP test cases and test structures, automates CAD workflows, supports extraction and simulation tools, resolves EDA and technology-file issues, documents processes, trains design engineers, and evaluates emerging EDA capabilities. The role collaborates with foundries, EDA vendors, and internal engineering teams to support physical verification and post-layout extraction.
Top Skills: CalibreFinfetGaaHspicePerlQrcQuantus QrcQuickcapRaphaelSkillSpectreStarrcTclUnix ShellVirtuoso
One Month AgoSaved
In-Office
River Hills, Austin, TX, USA
129K-207K Annually
Expert/Leader
129K-207K Annually
Expert/Leader
Software • Semiconductor • Manufacturing
Design, deploy, and optimize autonomous multi-agent AI architectures for semiconductor IP block development and support workflows. Integrate LLM orchestration and Model Context Protocol systems with enterprise verification frameworks to improve efficiency, quality, and automation across hardware engineering processes.
Top Skills: Artificial IntelligenceEnterprise Verification FrameworksLarge Language ModelsLlm OrchestrationModel Context ProtocolMulti-Agent AiSemiconductor Automation
One Month AgoSaved
In-Office or Remote
2 Locations
100K-160K Annually
Senior level
100K-160K Annually
Senior level
Software • Semiconductor • Manufacturing
Provides senior-level technical consulting for mainframe infrastructure environments and Broadcom Software products. Responsibilities include solution architecture, product implementation and upgrades, integrations, demonstrations, proofs of concept, troubleshooting, technical documentation, customer presentations, and post-implementation support. The consultant advises clients and management on infrastructure strategies and works with account teams to design solutions. Requires expertise in z/OS, Broadcom mainframe tools, REXX or HLASM, and major mainframe subsystems and security managers. Client-site travel is required.
Top Skills: Acf2Bmc Mainframe ProductsBroadcom Common ServicesBroadcom Mainframe Application TunerBroadcom NetmasterBroadcom Ops/MvsBroadcom SysviewCicsCobolDb2HlasmIbm Mainframe ProductsIbm MqImsJesRacfRexxRocket Mainframe ProductsTssVsamZ/OsZ/VmZ/Vse
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One Month AgoSaved
In-Office
River Hills, Austin, TX, USA
83K-132K Annually
Junior
83K-132K Annually
Junior
Software • Semiconductor • Manufacturing
Designs complex flip-chip BGA packages for high-performance ASICs used in AI, networking, HPC, and 5G applications. Responsibilities include package layout, signal and power integrity, thermal and reliability considerations, manufacturability, and design of SerDes, ADC/DAC, DDR, and related structures. The engineer manages multiple projects, collaborates with global teams and vendors, interfaces with customers, and improves design processes through automation and documentation. This is a fully onsite role.
Top Skills: 5G Rf/MicrowaveAdc/DacAllegro Package DesignerAsicCadence ApdCadence SkillDdr5Flip-Chip BgaHbmPower IntegritySerdesSignal Integrity
2 Months AgoSaved
In-Office
River Hills, Austin, TX, USA
122K-195K Annually
Senior level
122K-195K Annually
Senior level
Software • Semiconductor • Manufacturing
Design and architect high-speed 100G+ SerDes signal-processing systems, including equalizers, FEC, filters, modulation, and analog compensation. Develop MATLAB and C/C++ models, simulations, requirements, verification plans, firmware, and lab tests. Collaborate with analog, digital, RTL, firmware, and validation teams to implement and debug ASIC designs. Support communications standards development, customer meetings, technical documentation, and marketing collateral.
Top Skills: AsicCC++DspFecIeee 802.3MatlabOifPamPcie Gen6Pcie Gen7PllRtlSerdes
Reposted 2 Months AgoSaved
In-Office
River Hills, Austin, TX, USA
52-83 Hourly
Senior level
52-83 Hourly
Senior level
Software • Semiconductor • Manufacturing
Responsible for front end design and verification of ASIC design blocks, including architecture definition, logic design, synthesis, and verification through simulation and analysis of timing.
Top Skills: Cadence ConformalCadence Rtl CompilerGitPerlPrimetimeSpyglass LintSvnSynopsys Design CompilerSynopsys FormalityTclVerilog
2 Months AgoSaved
In-Office
River Hills, Austin, TX, USA
144K-230K Annually
Senior level
144K-230K Annually
Senior level
Software • Semiconductor • Manufacturing
Design and verify high-speed SerDes physical-layer algorithms and architectures (100G+). Develop bit-exact MATLAB and C/C++ system models, run system-level simulations, collaborate with analog/digital teams, perform lab validation and firmware/debug, document requirements and test plans, support standards and customer interactions.
Top Skills: CC++Cdr PllEqualization TechniquesFecIeee 802.3MatlabOifPamPcie Gen6Pcie Gen7Rtl (Hdl)S-ParametersSerdes
3 Months AgoSaved
In-Office
River Hills, Austin, TX, USA
122K-195K Annually
Senior level
122K-195K Annually
Senior level
Software • Semiconductor • Manufacturing
Design and deliver high-performance flip-chip BGA ASIC packages addressing signal integrity, power integrity, thermal, reliability, and manufacturability. Perform physical layout, manage multiple projects, interface with customers and vendors, and improve design processes and automation.
Top Skills: Adc/DacAllegro Package DesignerCadence ApdCadence SkillDdr5Flip-Chip BgaHbmSerdes (224G+)
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